The present exemplary embodiments relate to in-process intralayer defect detection and correction and interlayer shunt defect detection and correction. It finds particular application to Printed Organic Electronics (POE) arrays, but can be applied to a wide variety of electronic arrays including, for example, liquid crystal displays (LCD), memory arrays (RAM, ROM, etc.), printed circuit boards (PCB), active matrix displays, and passive matrix displays.
With respect to conventional array fabrication processes, forming patterns using traditional photolithographic mask printing methods is highly productive in producing parts that have the exact same pattern over and over again. With this approach, substrate die yield is highly dependent on the absence of process artifacts (i.e. particles etc). If these artifacts cause a line open in the electrical circuitry, repair by localized line reconnection is expensive, tedious, time consuming and may not be practical. Defective dies are usually marked and rejected after die dicing. When die size becomes very large, as in for example, a POE array or a flat panel display (FPD), rejecting such a large die (large real estate) can be very costly. Moreover, bad or poor NSN+ amorphous silicon chemical vapor deposition (CVD) sometimes makes the substrates un-testable as the matrix arrays become non-functional. In particular, process defects due to layer to layer electrical shunts can sometimes disable an entire read out chip making defect isolation and defect locating impossible. The chip, even if working, may produce unreliable results for detection purposes.
Traditionally, electrical evaluation of array matrices has been performed as a final step (as opposed to an in-process step) in the array matrix fabrication process and has been accomplished by contact or non-contact probing of I/O (input and output) pads that have been patterned and defined. A typical array matrix's large physical size can present quite a challenge for such a high I/O test pad connection count to the outside world. For example, most POE arrays have a very large number of DATA and GATE interconnect lines that require testing. In order to manage electrical testing on such a large physical substrate form factor, contact type probe card based testers such as those from Tokyo Cathode Laboratory and flying probe testers such as those from Acculogic have been used. However, these probe testers (or probers) are capital intensive and do not usually fully test the multilevel device matrix. Static multiple probe approaches (“bed of nail” type) have also been used. The apparatus described in U.S. Pat. No. 6,834,243 (“Apparatus and method for electrical testing of electrical circuits”) is an example that is suitable for high probe count electrical testing. However these “bed of nail” methods require custom fixturing for each device design and are hence very costly.
An example of a LCD panel final test is illustrated by the LCD evaluation method described in U.S. Pat. No. 5,081,687 and RE37,847. This evaluation method uses a video image capture method to detect FPD matrix electrical opens and shorts by comparing the newly acquired display pattern to a previously captured golden standard sample display image pattern result. For these types of measurement, the FPD is energized through contact type edge shorting bars. This approach is also capital intensive and requires the full process fabrication of the device matrix to the pixel level formation so that the LCD panel can be tested. Another approach for testing POE arrays uses an x-ray imaging system after the formation of the active matrix thin film transistors (TFTs). The x-ray images produced by the imaging system show horizontal and vertical defect lines. However, it is very difficult to quantify the exact cause of such line defects. For example, FIG. 1 shows an image test result 100 from an x-ray detector. As shown, locating the defect via this process can be difficult and time consuming.
Later developed processes utilize peripheral shorting bars and/or short circuit rings. For example, U.S. Pat. No. 7,330,583 (“Integrated visual imaging and electronic sensing inspection systems”) utilizes shorting bars to expand the video image capture method to various electronic sensing means such as voltage, e-beam and charge sensing. These shorting bars and/or short circuit rings can be classified into full ring structures or grouped into segmented shorting bar structures. The full ring structures are typically used for static electricity mitigation to protect the array matrix device pixels. An example of this is found in U.S. Pat. No. 5,650,834 (“Active-matrix device having silicide thin film resistor disposed between an input terminal and a short-circuit ring”), where silicided resistors positioned between the edge short circuit ring and the interior array matrix provide static electricity protection for the pixel thin film transistors (TFT).
Another example of an LCD panel final test evaluation is illustrated by Orbotech Ltd.'s evaluation method illustrated in U.S. Pat. No. 5,771,068 (“Apparatus and method for display panel inspection”). This final test evaluation used a full field image sensor to capture and analyze a FPD matrix that was stimulated with various pixel patterns.
Non-contact probing methods have also been used. U.S. Pat. No. 6,630,832 (“Method and apparatus for the electrical testing of printed circuit boards employing intermediate layer grounding”) used stimulating and sensing heads and various AC frequencies to probe printed circuit boards (PCBs).
The prior art methods mentioned above apply predominantly to the final stage of testing matrix arrays. Since matrix arrays become a high value added item when fabrication approaches the formation of array pixels, device rejection at this final test stage due to line open, line bridge (i.e. short), and shunt defects becomes very costly. It is thus desirable to have an in-process (or in-fabrication) approach to electrical testing for matrix arrays that is thorough and effective for open, short and shunt defect detection. The exemplary methods and systems utilize a hybrid static peripheral I/O connection method in conjunction with a dynamic probing scheme, an arrangement of sacrificial edge shorting bars (with or without cut lines), and an analytical method to determine defect type and defect locations. For these methods and systems, a previously measured golden standard reference sample result is not required.